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| Product Brief |
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Schematics For details of the CIII Decv Kit visit Cyclone III EP3C120F780 Dev Kit |
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HSMC DVI EDID Update This sof updates the EDID EEPROM on the HSMC DVI board to correctly report 1080P@50 |
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Altera DSP Video Processing Reference Design The AlteraŽ video and image processing example design demonstrates up conversion from a standard definition (SD) video stream in national television system committee (NTSC) format and picture-in-picture mixing with a background layer. |
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DVI 1080P Loop-through (Beta) This reference design demonstrates a DDR2 SDRAM loopthrough of a 1080P@50. An input image on the DVI port is tripple-buffered through the top and bottom banks of DDR2 SDRAM before transmitting on the DVI output port.
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Quad Video Mosaic This reference design takes four composite video inputs and displays a mosaic on the DVI output port |
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Optrex Display Driver This reference design shows how to drive the VDK Optrex LCD Screen |
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1080P Colour-Space-Conversion reference design (Beta) This reference design performs colour-space-conversion on a 1080P@50 input image stream. The input RGB stream is converted to YCrCb typically used on HDMI receivers. |
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1080P PiP Reference design (Beta) This reference design demos 1080P@50 Picture-in-Picture. A single Quad Video composite signal is superimposed on a 1080P background video stream. |
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NEW 1080P 4x PiP Reference design v8.1 This reference design overlays the 4 NTSC inputs onto a 1080P background image. Enhanced features of the v8.1 VIP Suit and the two independent DDR2 banks are exploited to achieve this outstanding demonstration of the VDK. Requires Quartus II version 8.1 |
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