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| Product Brief |
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| Schematics |
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HSMC DVI EDID Update
This sof updates the EDID EEPROM on the HSMC DVI board to correctly report 1080P@60 |
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DVI 1080P Loop-through CIV
This sof updates the EDID EEPROM on the HSMC DVI board to correctly report 1080P@60 |
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DVI 1080P Loop-through C120 (Beta)
This reference design demonstrates a DDR2 SDRAM loopthrough of a 1080P@60. An input image on the DVI port is tripple-buffered through the top and bottom banks of DDR2 SDRAM before transmitting on the DVI output port.
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DVI 1024x768 Loop-through C25 Eval (Beta)
This reference design demonstrates a DDR SDRAM loopthrough of a 1024x768 image. An input image on the DVI port is tripple-buffered through the boards DDR SDRAM before transmitting on the DVI output port.
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Stratix III Dev Kit Pin allocation Tcl scripts
These script files assign the DVI board pins for the Stratix III Dev Kit. See file contents for instructions. |
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